Research projects

With the increasing widespread use and popularity of cell phones, laptops and similar electronic mobile equipment, there is a subsequent rising need for faster operational speeds. At the same time, increasing amounts of energy are both being used and demanded. How to satisfy these growing needs through longer battery life is currently a major focus of research.
Power amplifiers (PAs) on wireless devices are causing endless problems for users of wireless telecommunication equipment due to their drain on the power system. Researchers are also looking into ways to increase the operational power-added efficiency (PAE) in amplifiers. With PAE increased, the device is able to output the same amount of power with less DC power consumed.
Non-linear Class-F and Class-F-1 PAs have drawn the most attention among all different classes of PAs from engineers because of their capability of outputting high power and providing good PAE. Class-F boosts up PAE by controlling the harmonic content at the output. Advanced Design System (ADS) from Agilent is used for design and simulation class F power amplifier based on the ADS model of Cree’s CGHV1J006D high electron mobility transistor (HEMT). A high efficiency power amplifier is fabricated on LTCC. In this design, the harmonics at the input are controlled as well as the harmonics at the output. An input wave-shaping network is designed to shape the waveforms at the gate. By terminating harmonics with proper impedances at the output, a square voltage waveform and a half-sine current waveform are obtained at the transistor drain terminal. The overlapping area between the voltage and current waveforms can be reduced as well as the active device power consumption.
The final design operating at 5 GHz produced a PAE of 72% with 38.50dBm output power in simulation and I am still measuring the results of fabrication.

The research focus on the embedded system for RF vector measurements in frequency agile and reconfigurable Front-Ends to be tuned and operate at the frequency of choice. This technique realise on measuring the amplitude and phase of two RF signals through two power detector circuits using four-port reflectometer which simulated by HFSS and fabricated by using LTCC martial. The proposed reflectometer consists of TL transmission line which connected to port 1( source) and port 2 (load), two vais (implement the sniffers) that placed close to TL and separated by the distance d, and two power detecting circuits (LTC558) which are placed at port 3 and 4 respectively. This reflectometer characterized by very small size and very low coupling (below -30 dB) so that become suitable for circuit integration and embedded measurement. This topology can be integrated in different application such as Six-port Technique and Monolithically Gain Phase Detection which require using directional coupler to sample the two waves for which the complex ratio is to be measured.


The proposed reflectometer on HFSS

Abstract
Nowadays, location-based services are integral part of everyday life. In addition, there are more and more GNSS constellations being deployed. This will help improve the accuracy and precision of positioning from some meters to some centimeters, in real-time and at any point on the Earth or on space. This involves sophisticated GNSS receivers which in turn require GNSS simulators able to generate a large number of GNSS signals from a variety systems, such as GPS, Glonass, Galileo, Compass (Beidou-2), QZSS etc., and their multipath components. In this context, simulators that use dedicated hardware, such as FPGAs, become too costly and may even not be feasible. This project will target ways to leverage the full power of commercial CPUs and GPUs to address this challenge. In order to accomplish this, issues related to computer hardware resource management, operating systems interrupts and constraints as well as software/hardware co-design will be investigated.