Research areas


Specific objectives

The research area addressed by the chair stems directly from the results of studies indicating that less than 40% of integrated circuits are perfectly operational on first use, and, among those that fail and require a new design iteration, over 70% face errors resulting from incorrect or incomplete specifications. The effectiveness of the verification process is also an issue. It should be noted that it is not at all unreasonable to assume that similar statistics could be obtained with highly integrated systems, since they share some characteristics with integrated circuits.

These statistics indicate two things:
  • Greater attention must be paid to specifications as well as to verification.
  • Most circuits must be diagnosed in order to isolate and correct any malfunctions sources.

Several other observations can be made:
  • With increasingly optimal integration, which includes sophisticated encapsulation techniques, testing and diagnosing embedded systems becomes more and more difficult, since access points are becoming increasingly scarce even as the number of points to be tested keeps growing.
  • The use of optimal integration is based on the assumption that the volume occupied or the dissipated power used should be optimized. This requirement is best served by proceeding with a more rapid exploration of the design space.


From these observations, it is clear that any methodology used with highly integrated and highly reliable systems must allow the following capabilities, which are also the specific objectives of the Chair:
  • P1) Ensure that specifications are complete and consistent.
  • P2) Improve the verification process.
  • P3) Allow a very rapid exploration of the design space for optimization.
  • P4) Facilitate diagnosis and shake-out.

Research areas

The following are the four primary research areas of the chair:

1 : Rapid test insertion-based design approach
The objective of this research axis is to design a systematic approach allowing specifications to be rendered more complete and consistent. The favored design approach is based on rapid test insertion, and consists in defining the tests to be conducted right from the start in order to confirm that the specifications have indeed been observed. The goal of this exercise is to very rapidly examine the specifications during the testing phase in order to better clarify and document them.

2 : Hierarchical and bidirectional multi-level representation reference graph with structural and state anchor points
The graph has already been used in the design process for several years. However, the format and structure of conventional graphs are not conducive to the achievement of the Chair's objectives, particularly due to their unidirectional (downstream) exploration and the absence of markers between the different abstraction levels.

The first objective of this research axis is to improve conventional graphs in order to assign them additional characteristics such as:
  • the possibility of simultaneously representing several levels of abstraction;
  • the possibility of inserting structural and state anchor points, with the anchor points serving as reference points when explored;
  • the possibility of exploring the graphs hierarchically and bidirectionally.

The second objective of this research axis is to create tools facilitating the viewing and manipulation of the graph.

3 : Dual partitioning/assembly for management of interfaces and specifications
This research axis tackles design from a new angle: that of the duality between partitioning and assembly. In fact when examined closely, design is seen as a succession of divisions of modules into partitions, which must then be assembled. This division gives rise to interfaces which, when ill- or incompletely defined, become a source of design errors. The goal of this research axis is to explore and exploit this duality.

4 : Intrinsic sensitivity of risk systems and factors
The weak spots that can be identified at higher abstraction levels constitute the information source that is currently underused in low-level abstraction verification processes (such as RTL). These weak spots are the operation points with the smallest margins when it comes to observing specifications. From a verification (and testing) perspective, these points are interesting because they are the weak links of the systems, and consequently, are the first to fail. They can easily serve as barometers for measuring risk factors against (dynamic) noise sources to which a system may be exposed, sources which are often neglected in the (simplifying) hypotheses underlying modeling. The objective of this research axis is to systematically exploit system weak points identified at high levels in order to direct verification, testing and diagnosis efforts.